When designing integrated circuits, electronics engineers typically determine the size and placement of drivers based on design requirements and using various integrated circuit layout tools. When a proposed layout design is complete, a thermal analysis is conducted of the integrated circuit device to ensure that the driver locations have been properly specified. Typically, the thermal analysis is performed by using a finite element analysis program. The finite element analysis indicates whether the amount of power dissipated in the integrated circuitry, or the size or location of the drivers, can potentially lead to thermal overload of the integrated circuitry.
In order to conduct a finite element analysis, the final integrated circuit layout is used to construct a three-dimensional model of the integrated circuit. For this to occur, a data exchange must take place between the integrated circuit design tools and the finite element analysis tools. The data exchange is typically cumbersome and can be very time-consuming. Specifically, an analyst must define the areas on the surface of the die that have individual drivers and input that information into the finite element analysis tool. The analyst may complete this process using one of two conventional methods. The analyst can either manually enter the information or enter the information by reading an intermediate format file such as an Initial Graphics Exchange Specification (IGES) file. When the information is entered manually, a large number of coordinate pairs describing the driver boundaries are typed into the finite element analysis tool. Accordingly, the likelihood of typing an inaccurate number in a coordinate pair is relatively high. The second method, reading an intermediate format file, generally includes spending a considerable amount of time cleaning up the intermediate format file data so that the finite element analysis tools can read the data.
After the layout data has been successfully imported into the finite element analysis tool, a three-dimensional mesh is generated. The three-dimensional mesh is generated before the thermal analysis is performed. Oftentimes, before an integrated circuit is constructed, changes in customer requirements or other fabrication modifications can lead to changes in the integrated circuit layout. Consequently, it is important for this process to be completed in a timely and efficient manner with minimal likelihood of error so that designers, as well as customers, are aware of the effect of modifications requested during fabrication.
Accordingly, a method of conducting a finite element analysis that minimizes the likelihood of human error and can be completed in relatively minimal time would prove useful, and would be an improvement in the art.